1. Field of the Invention
Exemplary embodiments of the present invention relate generally to a multi-chip package, a semiconductor device used therein, and manufacturing method thereof.
2. Description of the Related Art
In recent years, with the rapidly increasing demand for portable electronic products, the demand for thin, small and/or lightweight elements mounted in the portable electronic products has increased.
Conventionally, there may be ways to attain the thin, small and/or lightweight elements, including, for example, shrinking the physical size of a discrete element, integrating multiple individual elements into a single chip (e.g., a system-on-a-chip (SOC) technique), and/or integrating multiple individual elements into a single package (e.g., a system-in-package (SIP) technique).
Further, the SIP technique may be similar to another conventional technique called multi-chip module (MCM), in which multiple silicon chips may be horizontally or vertically mounted in a single package. Thus, according to the conventional MCM technique, the multiple chips may be mounted generally in a horizontal direction, whereas in the SIP technique, the chips may be generally mounted in a vertical direction.
Further, if a radio frequency (RF) chip, which may be smaller than a logic/memory chip stacked on a large-sized chip, is employed, the length of connectors, such as bonding wires of the RF chip may need to be longer. This may reduce performance of the RF chip and may generate a crosstalk between the RF chip and the large-sized chip.
Thus, when stacking a plurality of chips in a perpendicular direction, the RF chip may generally be placed at the bottom of the stack.
In a case where the size of an upper semiconductor chip may be larger than that of a lower semiconductor chip, or when two rectangular semiconductor chips having relatively the same size and area may be stacked in a crosswise manner, then the wire-bonding chip pads located in a hang-over portion (e.g., a portion of the upper chip which is not supported by the lower chip) of the upper semiconductor chip may develop defective cracks, for example, due to the contact impact of a bonding capillary and/or during a wire-bonding process.